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New architecture of the Pentium 4

New architecture of the Pentium 4

Tomorrow the time has come, the IDF (Intel Developer Forum) will take place in San Jose. And since it doesn't take too long until the Pentium4 is officially launched, Intel is also providing information about the processor's architecture. The fact is that the P6 design is a thing of the past.

Intel has been using this architecture since 1995 and the Pentium Pro, now it's over. The new architecture is called 'NetBurst', the big innovations include the abolition of the instruction cache and a new method of intermediate storage of up to 12,000 internal microcodes. Furthermore, the Pentium 4 has a 20-stage pipeline, which enables up to 126 commands to be received at the same time, three times as many as with P6 processors (e.g. Pentium3 and Celeron2). In addition, there are the 144 new commands (SSE2), which serve as a supplement to MMX and SSE. The bandwidth of the L2 cache is particularly impressive, it is a full 48 GB/sec for a P4 with a 1.5 GHz processor clock.

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