Intel's processor history: the path from the Intel 4004 to the Pentium 4

Intel's processor history: the path from the Intel 4004 to the Pentium 4

1998: Intel's budget CPU: The Celeron

Since the sales figures of the Pentium II had to admit defeat, at least in the low-end segment, AMD's K6 series, Intel announced in January a Pentium II processor for the 'basic PC' that does not have an L2 cache but should be based on the Deschutes core. So he did without the very same feature that Intel introduced with the Pentium Pro and then with the Pentium II. In addition, it was only operated with a front-side bus of 66 MHz. As the name 'Celeron' suggests (English 'celerity' = speed), it should offer fast performance in the low-cost area at low prices. But the first Celeron, code nameCovington, which was initially clocked at 266 MHz and came onto the market in April 1998, could not hold its own. In a direct comparison it was defeated by the slower clocked competitors from AMD and the Pentium 233 MMX. Even a Pentium 200 MMX could hold its own against the first Celeron and was cheaper.

Intel Celeron SECC
Intel Celeron DIE

Intel recognized that you couldn't win a flower pot without an L2 cache and gave the Celeron a slimmed-down L2 cache in August. The second Celeron, developed under the code name Mendocino, now had a 128KB L2 cache and was particularly popular with gamers because of its low price and excellent overclockability. The Mendocino was produced with clock frequencies of 300 to 533 MHz. The 533 MHz fast and last version did not appear until January 2000. Since the L2 cache of the Celeron could be integrated directly into the CPU and the SEC housing was thus unnecessary because the CPU board was almost completely empty, Intel provided the Celeron for the PPGA format. The Celeron with 300 MHz and 128KB L2 cache was officially called the Celeron 300A when it was launched, while the version without L2 cache was still offered as the Celeron 300. All versions over 300 MHz dispensed with the additional abbreviation 'A', since they were only produced with an integrated L2 cache.