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Initiative for 1 TB/s storage from Rambus

Initiative for 1 TB/s storage from Rambus

According to a report by TG Daily, storage specialist Rambus is planning an initiative for storage with a theoretical total bandwidth of one TB per second. The 'Terabyte Bandwidth Initiative' (TBI) is to be presented on Wednesday and will provide future manycore architectures with sufficient bandwidth.

Rambus will probably rely on 16 parallel DRAM channels, each with 16 Gbps and 4 Bytes of data work per clock and thus bring it to a theoretical total bandwidth of one terabyte per second. Each of the channels would serve a group of several computing cores directly. According to TG Daily, there should not yet be a fully functional prototype. However, Rambus has a prototype made in 65 nm, which with one memory channel already achieves the estimated bandwidth of 64 GB/s.

Several connections (the final system should have 16) with 32 times the speed connect the memory controller with the DRAM chips. Two connections are shown here. (Image: TG Daily)

To set the clock frequency of 16 Gbps per channel Rambus should use the PLL -based FlexLink timing system on the chips. The PLL increases the input clock rate of 500 MHz to 32 times the transmission rate of 16 Gbps. In addition, for the first time, a fully differential memory architecture (FDMA) is being used for the signal system (command/address, data and clock signal), which together with Rambus' FlexPhase technology, which precisely synchronizes the high clock frequencies with the data should keep the number of transmission errors low despite the high clock rates. Furthermore, Rambus is said to have redesigned the command/address bus. In contrast to current DRAM chips with twelve connectionsBetween DRAM and controller, TBI should use only two connections, scalable as required, but these also work at a 32-fold clock. This is primarily intended to enable cheaper ' System on Chip ' systems and at the same time increase support for different granularities (i.e. how much memory is accessed per request, typically 64 or 128 bytes). Due to the additional bandwidth of the 32-fold connection, lower granularities should be possible without affecting throughput or latency.

Rambus is said to have targeted mass production of the new memory for 2010 or 2011, with power consumption and the associated heat development currently being Should represent major problems. Therefore, the first products would have to be manufactured at least in the 45 nm process. Further information on the Terabyte Bandwidth Initiative will be available on Wednesday at the Rambus Developer Forum in Tokyo.

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