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Duron 950 to Athlon XP 1.7+ in the test: AMD processor Roundup

Duron 950 to Athlon XP 1.7+ in the test: AMD processor Roundup

Technology

AMD itself summarizes all performance-increasing architecture innovations of the Palomino under the term 'QuantiSpeed ​​architecture'. Intel also has a catchphrase for the performance of the P4 with the 'Netbrust Technologie'. The QuantiSpeed ​​architecture occupies a key position in AMD's marketing for the Athlon XP and represents the basis or justification for the introduction of model numbers apart from the real processor clock, i.e. the performance rating. We will therefore give this QuantiSpeed ​​architecture a separate section .

Athlon Model 4 System Block Diagram
Athlon Model 6 System Block Diagram

QuantiSpeed ​​architecture

If you have dealt a little with the 'QuantiSpeed ​​architecture', you will soon be faced with an understanding problem. Due to the similar cores of the Morgan and the Palomino, the term QuantiSpeed ​​architecture should actually apply fully to the new Duron (Morgan) as well as to the Mobile Athlon 4 (Mobile Palomino) and the Athlon MP (Multiprocessor Palomino). However, this name is neither used in the mobile Athlon 4 nor in the Duron. Also in the Athlon MP Processor Model 6 Data Sheet from June 2001 no trace of this term can be seen. Only with the Athlon MP Processor Model 6 OPGA Data Sheet from December 2001 did AMD use the term QuantiSpeed ​​architecture here as well. Since there were no further fundamental modifications to the processor apart from the new housing in the period of six months between these two documents, it can be assumed that the processor manufacturer from California must have re-created the term during this period. Since the Athlon MP in the OPGA (Organic Pin Grid Arry), like its Palomino brothers, can be identified by model numbers and no longer by the real clock, the theory seems that the QuantiSpeed ​​architecture should serve as a reason for the introduction of the performance rating, to confirm.

What does the QuantiSpeed ​​architecture really include? Above all: is it actually a new architecture, or just a new 'TradeMark ™', a name that is used as part of a strategy for marketing the performance ratingwas created?

According to AMD, the QuantiSpeed ​​architecture consists of four core elements (partly freely translated):

  • The nine-fold, pipeline-supported, superscalar x86 processor micro-architecture that provides an optimal balance between work per clock cycle and frequency scalability. It is made up of three pipeline-supported, superscalar floating point execution units, integer units and address calculation units.
  • The 3DNow! Professional-capable floating point unit should be the fastest available today.
  • A new type of hardware-based advance data access (data pre-fetch) which is intended to improve the performance of demanding software in particular by using high available memory bandwidths.
  • Improved exclusive and speculative two-level translation look-aside buffers (TLB) are intended to prevent the processor from stalling while it is waiting for future data and/or instructions.

If you take a closer look at these key features of the QuantiSpeed ​​technology specified by AMD, it becomes clear that some old acquaintances are hidden behind the new name. The “nine-fold, pipeline-based, superscalar x86 processor micro-architecture” corresponds in principle exactly to that of the Thunderbird. Regarding the second point listed, it must be said that the floating point unit of the Athlon XP (Palomino) is also similar to that of the Thunderbird Athlon, but here, as already mentioned, the expansion of the command sets by the 52 SSE1 commands promises a little additional performance. Point 3, on the other hand, promises a really big step forward in terms of performance, ie the hardware data pre-fetch implemented on the hardware side, which Intel already introduced with the PIII and its 'Data Prefetch Logic' and which the Palomino now also masters. Following the current command sequence, the pre-fetchTechnology from AMD soon needed data from the main memory in the much faster on-the-level 2 cache so that it can be fed to the processor without delay when it is needed. At least the objective of the fourth and last listed QuantiSpeed ​​element sounds similar, which is also not an absolute innovation, but an improvement of an already known technology. The use of a further developed translation look-aside buffer (TLB) is intended to prevent the processor from having to wait for data/instructions. The principle that this goal is to be achieved differs significantly from that of data pre-fetching. The TLB does not hold the data itself, but, to put it simply, the route to them or “maps” containing the route; in English, i.e. maps too frequently and data/instructions used in the recent past are stored in the TLB. More precisely, these maps form the link between the logical memory addresses of the data (known to the processor and output by the program) and the physical memory addresses (required by the processor). In the TLB, the physical addresses for the most frequently used data are always kept ready. This eliminates the time-consuming conversion from logical to physical addresses. With the Athlon XP, three specific improvements to this technology should contribute to the performance increase. First, the Level 1 data TLB has been increased from 32 to 40 entries. Second, according to AMD, the “exclusive buffer” structure of the level 2 data and instruction TLBs now removes duplicate data, which frees up level 2 cache for other data. Thirdly, the 'speculative generation and loading' of new maps should also accelerate the TLB and thus the Palomino.

Let us recapitulate the material we have just derived. Even if the Athlon XP is expanded in some places (data prefetchLogic) or supplemented (Translation Look-aside Buffers), the term 'QuantiSpeed ​​Architecture' is more likely to be seen as a powerful argument for the P-Rating and the performance gains achieved. In the end, a real innovation is only hidden behind one of the sub-items and this applies equally to the new Duron, the Athlon 4 and the Athlon MP.

On the next page: Temperature Diode