AMD's Spider platform in the test: CPU + chipset + graphics card
The CPU: Phenom
Already in November 2006 the first quad-core processor for the desktop area saw the light the world - the chip had the code name Kentsfield and came from Intel. After a year now, AMD wants to stand up to the competition with its own quad-core creation called Phenom (code name Agena).
However, the implementation approach is fundamentally different: while Intel has two dual-core Processor dies (Core 2 Duo, code name Conroe) coupled together on a processor housing (multi-chip package, MCP), AMD is - from its own point of view - one step further and offers a native quad-core processor. The Phenom was developed in Austin, Texas. It is manufactured in Dresden using the 65 nm process. In the course of the next year - as is already the case with Intel - they want to switch to the 45 nm lithography process.
The TDP of the Phenom 9500 and 9600 is 89 watts. Each individual core has 512 KB of L2 cache. In addition, the entire processor has a shared L3 cache with 2 MB, which is shared by the cores. However, AMD has reached into its bag of tricks when it comes to the memory hierarchy. The L1 cache prefetchers can request data from the main memory without the usual detour via the L2 and L3 cache.
The processor-internal data paths as well as the execution units for SSE and FPU have been changed from 64 bits to 128 bits (as with Intel's core microarchitecture) doubled. This means that SSE commands can now be processed within one cycle. AMD's architecture allows the execution of two SSE commands in parallel - Intel is still a step ahead with three execution ports for SSE (not all ports can execute all SSE commands). The Phenom's instruction fetch buffer has been expanded to a width of 32 bytes. This means that more x86 instructions between three and 15 bytes long fit into the instruction fetcher, the first part of the instruction pipeline. This ensures, even with the longer 64-bit commands (on average approx. 4.5 bytes), that the processor, which is still 3 times the super-scaled, is supplied with enough commands for processing. Intel's pipeline front end reads (since the Pentium Pro) only 16 bytes from the instruction cache and thus runs the risk of not being able to provide the quadruple superscalars with enough work, especially with 64-bit code.
The jump prediction was also made by AMD improved and provided with a new logic. Accurate branch prediction is important, since modern processors process several instructions in parallel and a branch that does not behave as predicted makes the other instructions executed in parallel on suspicion void. The virtualization technology has been improved so that the hypervisor can make their memory pages available to the guest systems more quickly. The speed of the memory controller still integrated at AMD has been increased from DDR2-800 to DDR2-1066. The function block contained in the silicon also supports DDR3 up to 1600 MHz(effectively). However, AMD has not yet made use of this.
With the Phenom, AMD is also taking the step towards the industry standard HyperTransport 3.0 (HT 3.0), which offers significantly higher bandwidths. Theoretically, this high-speed connection can transfer up to 20.8 GB/s. According to AMD, the Phenom can currently use up to about 18 GB/s and these values should increase with higher clock rates. With all of this, the Phenom remains backwards compatible with the older HyperTransport 1.0 with only about 6.4 GB/s bandwidth.
AMD has also taken care of the energy requirements of the Phenom thought. AMD calls the “split power lane” the option of supplying the memory controller and the CPU cores with two independent voltages. With the power state C1E, which the Phenom now also supports, AMD fulfills the Energy Star 4.0 specifications that have been in effect since the middle of the year.
Now the Phenom is no longer a newcomer to many users of price comparison services. The new CPUs have been listed by various dealers for days, of course without any availability. Much more interesting, however, is the pricing of these early offers. While the Phenom 9500 is currently (18.11.) On sale from 219.00 euros and the Phenom 9600 is expected to cost a proud 245.00 euros, the Phenom 9700, which has not even been launched today (see next paragraph), is being presented for 259.00 euros. Without a lot of words, we just want to show the pricing of AMD presented to the press.
Last but not least, we do not want to hide from readers why the planned and already mentioned Phenom 9700, according to AMD, will probably only be released in theJanuary 2008 will hit the market. The fault is an error in the processor, an errata. Such errors are nothing new to such a complex object as a microprocessor. The well-known Pentium was also plagued by such a bug and there are also many bugs slumbering in Core 2 and Athlon 64, which only mean a problem under very rare constellations. According to AMD, the error only occurs in extremely rare cases under full load and at high processor frequencies. When we asked, Dave Everitt explained that there was an error in the TLB of the L3 cache.
The TLB ensures the high-performance conversion - as it is implemented in hardware as a cache the virtual memory addresses used by applications into physical memory addresses. AMD would like to provide a tool and/or BIOS update with which the TLB of the L3 cache can be switched off. Switching off the TLB leads to a loss of performance of around ten percent.
On the next page: The chipset: 7-Series