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AMD shows Quad-Opteron System

AMD shows Quad-Opteron System

For the first time, AMD is presenting a test system with its new Opteron CPU to the public at Computex 2002 in Taipei. The Quad-Opteron system ran under the 64-bit Linux version from SuSE. However, AMD did not provide any information about the speed of the CPU or the performance in benchmarks.

There are some more details about this became known to the Opteron. The L1 cache, which is divided equally into instruction and data cache, has a total of 128 KB. The L2 cache should be up to 1 Mbyte in size. The memory controller integrated in the Opteron delivers up to 8.4 GByte/s with DDR266 and up to 10.8 GByte/s with DDR333 modules via a two-channel DDR interface. He alone should give the Opteron 20 percent more power compared to the previous AthlonXP. The instruction set of the Opteron naturally includes the new x86-64 instructions and the SSE2 instructions used by Intel for the Pentium4. As was already known, the three HyperTransport channels can each transmit a maximum of 6.4 GByte/s. Up to eight Opteron CPUs can be connected directly via hyperlink. So far, AMD had only presented single and dual systems, at Computex the next higher variant with four CPUs followed. AMD continues to announce the Opteron for the first half of 2003 and the ClawHammer for the fourth quarter.

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